1. Field of the Invention
The present invention relates to a semiconductor logic operating circuit and, more specifically, to a structure of a BiCMOS logic integrated circuit incorporating a bipolar transistor, an n channel insulated gate type field effect transistor and a p channel insulated gate type field effect transistor.
2. Description of the Background Art
A BiCMOS circuit incorporating a bipolar transistor and a CMOS transistor has been widely used for realizing high speed operation and low power consumption, utilizing the high speed operation performance of the bipolar transistor and low power consumption performance of the CMOS transistor (Complimentary Insulated Gate Type Field Effect Transistor).
FIG. 1 shows a circuit arrangement of a conventional BiCMOS logic circuit shown in, for example, Japanese Patent Laying Open No. 59-19435. The logic circuit shown in FIG. 1 forms an inverter circuit.
Referring to FIG. 1, the conventional BiCMOS inverter circuit comprises a p channel insulated gate type field effect transistor (hereinafter referred to as a pMOS) 42 and an n channel insulated gate type field effect transistor (hereinafter referred to as an nMOS transistor) 43 for inverting an input signal applied to an input terminal 10, and a pnp bipolar transistor 45 and an npn bipolar transistor 46 for driving charging/discharging of an output terminal 17.
The pMOS transistor 42 has its source connected to a first supply potential Vcc through a resistance 41 and to a base of the pnp bipolar transistor 45, its drain connected to a collector of the pnp bipolar transistor 45 and to the output terminal 17, and its gate connected to the input terminal 10. The nMOS transistor 43 has its drain connected to the output terminal 17, a collector of the npn bipolar transistor 46 and to the drain of the pMOS transistor 42, its source connected to a second supply potential V.sub.EE through a resistance 44 and to a base of the npn bipolar transistor 46, and its gate connected to the input terminal 10.
The pnp bipolar transistor 45 has its emitter connected to the first supply potential Vcc, its collector connected to the output terminal 17, and its base connected to the first supply potential Vcc through the resistance 41. The npn bipolar transistor 46 has its collector connected to the output terminal 17, its emitter connected to the second supply potential V.sub.EE, and its base connected to the second supply potential V.sub.EE through the resistance 44. The resistances 41 and 44 provide bias between the base and the emitter of the pnp bipolar transistor 45 and of the npn bipolar transistor 46, and supplies current to the bases of the transistors, respectively.
The operation will be described. FIG. 2 is a table showing ON/OFF states of the transistors and the input/output logic values of the circuit shown in FIG. 1. Now, let us assume that a logic value "0", that is, the potential level "L" is applied to the input terminal 10. In that case, the pMOS transistor 42 is turned on, while the nMOS transistor 43 is turned off. Since the pMOS transistor 42 is turned on, a current flows through the resistance 41 and through the transistor 42 to the output terminal 17. At this time, the base potential of the pnp bipolar transistor 45 falls from the first supply potential Vcc level, the base-emitter of the pnp bipolar transistor 45 is biased in the forward direction, and the pnp bipolar transistor 45 is turned on.
Meanwhile, since the nMOS transistor 43 is off, the base and the emitter of the npn bipolar transistor 46 are short circuited through the resistance 44, and since no base current is supplied thereto, it is turned off.
Consequently, the output terminal 17 is supplied with the current from the first supply potential Vcc through the pnp bipolar transistor 45 and the pMOS transistor 42. Generally, a bipolar transistor is capable of supplying large current. Therefore, the output terminal 17 is charged at high speed, and the potential thereof is increased. Finally, the potential level of the output terminal 17 reaches the first supply potential Vcc level, by the function of the resistance 41, that is, the function to operate the transistor 45 in a saturation region. Accordingly, when a signal having the logic value "0" is applied to the input terminal 10, a logic value "1" (potential level "H") is outputted at the output terminal 17.
When the logic value "1" is applied to the input terminal 10, the pMOS transistor 42 is turned off, and the nMOS transistor 43 is turned on. When the pMOS transistor 42 is turned off, the base and the emitter of the pnp bipolar transistor 40 are short circuited through the resistance 41, and since the base current is not supplied thereto, the pnp bipolar transistor 45 is turned off.
Since the nMOS transistor 43 is on, the collector-base of the npn bipolar transistor 46 is short circuited through the on resistance of the transistor 43, a current is supplied from the output terminal 17 to the base of the npn bipolar transistor 46, and the base-emitter thereof is biased in the forward direction by the resistance 44 to be turned on. Consequently, the potential at the output terminal 17 is discharged at high speed through the npn bipolar transistor 46, and the potential thereof falls. Finally, the potential level of the output terminal 17 reaches the level of the second supply potential V.sub.EE by the function of the resistance 44 to operate the transistor 46 in the saturation region. Accordingly, when the logic value "1" is applied to the input terminal 10, the logic value "0" is transmitted to the output terminal.
Generally, a bipolar transistor has parasitic capacitances between the base and the emitter and between the base and the collector derived from junction capacitances, interconnection capacitances or the like, as shown by the dotted line in FIG. 1. Similarly, MOS transistor has the parasitic capacitances between the gate and the source and between the gate and the drain thereof. Therefore, when the potential level of the output terminal 17 changes from "1" ("H") to "0" ("L"), the output terminal 17 and the base of the pnp bipolar transistor 45 is capacitance-coupled through the parasitic capacitance, so that a current flows through a path formed of the resistance 41-parasitic capacitance-the output terminal 17 or the first supply potential Vcc-parasitic capacitance-output terminal 17, for example, and as a result, a base current flows to the pnp bipolar transistor 45. Since the npn bipolar transistor 46 has been changed to the on state at this time, there exists a period in which the pnp bipolar transistor 45 and the npn bipolar transistor 46 are both on, a through current flows from the first supply potential Vcc to the second supply potential V.sub.EE and the power consumption is increased. The problem of the through current is of great significance especially when the logic circuit is operated at high speed.
In order to avoid this problem, the resistance value of the resistance 41 may be decreased to reduce the base current of the transistor 45. When the potential level of the output terminal 17 changes from "0" to "1", it is necessary to turn the transistor 45 sufficiently into the on state by lowering the base potential of the pnp bipolar transistor 45 sufficiently and by supplying a large base current. However, as the resistance value of the resistance 41 is made smaller, the base potential is set high even if the pMOS transistor 42 is on. Consequently, the pnp bipolar transistor 45 is not sufficiently turned on and the base current thereof becomes smaller, so that the ability of supplying current thereof is decreased, the output terminal 17 can not be charged at high speed, and the high speed operation becomes impossible.
If the resistance value of the resistance 41 is made larger, the base current of the pnp bipolar transistor 45 is increased, so that the current handling capability of the transistor 45 may be improved. However, there arises a problem of a large through current. Accordingly, it is necessary to set the value of the resistance 41 at an appropriate value in order to reduce the through current while maintaining the capability of driving of the pnp bipolar transistor 45, which is a difficult task. Especially when the manufacturing parameters of respective elements are different in different devices, it is impossible to set the resistance value of the resistance 41 at an appropriate value common to all the devices, and therefore a highly reliable semiconductor logic circuit can not be provided.
In addition, since the carriers in the pnp bipolar transistor are holes, the operational characteristics (speed of operation, capability of supplying current) thereof are in general inferior to those of the npn bipolar transistors in which the carriers are electrons. Therefore, in the circuit structure shown in FIG. 1 in which the pnp bipolar transistor 45 is used for an element for pulling up the output terminal, the rising characteristic of the voltage at the output terminal 17 is degraded.
Even if the gate width of the pMOS transistor 42 is enlarged to increase the conductance of the transistor 42 so as to compensate for the current supplying capability of the pnp bipolar transistor 45 by the utilization of the current supplying capability of the pMOS transistor 42 in order to improve the voltage rising characteristic at the output terminal, the ratio of the sizes of the pMOS transistor 42 and the nMOS transistor 43 at the input portion (ratio of the gate width, or the ratio of the gate width/gate length) is different, and therefore the input logic threshold value of the logic circuit becomes different.
In addition, since the potential of the output terminal 17 is made fully swung between the first supply potential Vcc and the second supply potential V.sub.EE by using the resistances 41 and 44 and emitter grounded output driving transistor 45 and 46, it takes a long time until the potential of the output terminal 17 is established, which reduces the speed of operation of the logic circuit.
Japanese Patent Laying Open No. 54-14869 discloses an inverter circuit comprising collector grounded npn bipolar transistor and pnp bipolar transistor for driving the output and an CMOS inverter for driving these bipolar transistors in response to an input signal. The speed of operation of this circuit is not very high, since the output voltage thereof is fully swung between +V and -V.
Japanese Patent Laying Open No. 60-125015 discloses a BiCMOS inverter comprising totem-pole connected npn bipolar transistors for driving the output and MOS transistors for drawing out electric charges of the bases of these bipolar transistors in response to an input signal.